The present invention relates, in general, to electronics, and more particularly, to semiconductor packages, structures thereof, and methods of forming semiconductor packages.
Electronic devices, such as semiconductor dies are conventionally enclosed in package structures that protect the semiconductor die from hostile environments and that enable electrical interconnection between the semiconductor die and a next level of assembly, such as a printed circuit board (“PCB”) or motherboard. The elements of a typical package structure include a conductive leadframe or substrate, an integrated circuit or semiconductor die, conductive structures, such as bond wires or solder balls that electrically connect pads on the semiconductor die to individual leads of the leadframe or substrate, and a hard plastic encapsulant material that covers the other components and forms an exterior of the semiconductor package commonly referred to as the package body. Portions of the individual leads are configured to electrically connect the package structure to the next level assembly.
In the past, certain reliability issues have plagued packaged electronic devices particularly in chip-scale packaged electronic devices having a high density of interconnects in a small footprint package. Such reliability issues have included, for example, poor bonding between the package electronic device and solder materials used to connect the packaged electronic device to a next level assembly and as well as other stress induced failures.
Accordingly, it is desirable to have a structure and method for forming packaged electronic devices that reduce the occurrence of reliability issues, such as those described previously. It is further desirable for the structure and method to be cost effective and manufacturable.
For simplicity and clarity of illustration, elements in the figures are not necessarily drawn to scale, and the same reference numbers in different figures denote generally the same elements. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. In addition, the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including,” when used in this specification, specify the presence of stated features, numbers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, and/or groups thereof. It will be understood that, although the terms first, second, etc. may be used herein to describe various members, elements, regions, layers and/or sections, these members, elements, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one member, element, region, layer and/or section from another. Thus, for example, a first member, a first element, a first region, a first layer and/or a first section discussed below could be termed a second member, a second element, a second region, a second layer and/or a second section without departing from the teachings of the present disclosure. Additionally, descriptions and details of well-known steps and elements are omitted for simplicity of the description. It will be appreciated by those skilled in the art that words, during, while, and when as used herein related to circuit operation are not exact terms that mean an action takes place instantly upon an initiating action but that there may be some small but reasonable delay, such as propagation delay, between the reaction that is initiated by the initial action. Additionally, the term while means a certain action occurs at least within some portion of a duration of the initiating action. The use of word about, approximately or substantially means a value of an element is expected to be close to a state value or position. However, as is well known in the art there are always minor variances preventing values or positions from being exactly stated. Unless specified otherwise, as used herein the word over or on includes orientations, placements, or relations where the specified elements can be in direct or indirect physical contact. Unless specified otherwise, as used herein the word overlapping includes orientations, placements, or relations where the specified elements can at least partly coincide or align in the same or different planes. It is further understood that the embodiments illustrated and described hereinafter suitably may have embodiments and/or may be practiced in the absence of any element that is not specifically disclosed herein.